verilog sample 코드

verilog 에서 test bench 내용 

트레이닝 삼아 짜봤는데 .. 내가 verilog 까지 하게 될줄이야 ..

본문 내용은  다음에 

always @(posedge clk)

  if(valid)

begin

  fdv_in=  $fopen("input.txt", "r");

  fdv_out=  $fopen("output.txt", "r");

    f_result = $fopen("result.txt", "w");

fvarerr = fdv_in && fdv_out;

if(fvarerr)

$display("success file open");

    else 

$finish;

  while(!$feof(fdv_out)) 

   

begin 

  code = $fscanf(fdv_in,"%h %h %b\n", addr_in, wdata_in, rw_in);

  code = $fscanf(fdv_out,"%h %h %b\n", addr_out, wdata_out, rw_out);

       

      $display ("address [%h] expect data  => %h result => %h", addr_in, wdata_in, wdata_out);

`ifdef RESULT_FILE

       if(wdata_in !== wdata_out) 

begin

      $display ("read addr => %h read => %h", addr_out, wdata_out);

$fwrite(f_result, "%8h %h %b \n", addr_out, wdata_out, rw_out);

end

`endif

    end //while end//

$fclose(fdv_in);

    $fclose(fdv_out);

    $fclose(f_result);

$finish;

end

endmodule